Intel has detailed the package design of its next-generation Xeon 7 "Diamond Rapids" server processor, which is designed to scale up to 256 P-cores and 1.28GB of shared last-level cache per socket. Built entirely on Intel's own foundry nodes, the chip is aimed at enterprise-scale agentic AI workloads and is positioned to match AMD's upcoming EPYC Venice in core count.
Intel used a presentation at Hot Chips to detail the package design of its upcoming Xeon 7 "Diamond Rapids" server processor, according to TechPowerUp. The chip is built around a disaggregated design similar in philosophy to AMD's EPYC chiplet approach: 16 core chiplets, each containing 16 "Panther Cove" P-cores, are mounted on four compute base tiles using Foveros 3D Direct hybrid bonding, with each base tile housing a shared 320MB L3 cache pool. Two Fabric Hub Tiles handle memory and I/O, together supporting up to 16 channels of DDR5 MRDIMM memory and PCIe Gen 6 connectivity. Notably, every tile in the package — core chiplets, base tiles, and fabric hubs — is fabricated on Intel's own foundry nodes (18A-P, 3-T, and 3, respectively), with no external foundry dependency.
On the core-count front, Wccftech reports that Diamond Rapids was originally planned with far more ambitious 384- and 512-core high-density variants using E-cores, but those plans were reportedly cancelled, leaving only the P-core lineup. The flagship P-core SKU is said to top out at 256 cores, a roughly 50% increase in core density over the current Granite Rapids "Xeon 6900P," which maxes out at 128 cores. That 256-core figure isn't official yet, since the lineup hasn't formally launched.
The core-count target appears aimed squarely at AMD, whose upcoming EPYC Venice ('Zen 6') lineup includes a 256-core EPYC 9996 and a 192-core EPYC 9966 SKU. According to Wccftech, AMD already has Zen 6 in volume production on a 2nm node, while Diamond Rapids is planned for 2027 on Intel's 18A-P process — meaning Intel still has ground to cover on timing, and the real test will be how Diamond Rapids performs and scales once it ships against AMD's already-shipping silicon.
What We Know
| Spec | Detail |
|---|---|
| Max Core Count | Up to 256 P-Cores (Panther Cove architecture) |
| Max L3 Cache | 1280 MB (320MB per base tile x4) |
| Core Chiplet Node | Intel 18A-P |
| Base Tile Node | Intel 3-T |
| Fabric Hub Tile Node | Intel 3 |
| Memory Support | Up to 16-Channel DDR5-8000 MCR-12800 |
| PCIe Support | PCIe 6.0 (128 lanes) |
| Expected Launch | 2027 |
Frequently Asked Questions
How many cores will Intel Xeon 7 Diamond Rapids have?
Intel's design goal is up to 256 P-cores per socket, built from 16 core chiplets each containing 16 "Panther Cove" P-cores, according to TechPowerUp's coverage of Intel's Hot Chips presentation.
What manufacturing process is Diamond Rapids built on?
The core chiplets use Intel's 18A-P node, the base tiles use Intel 3-T, and the Fabric Hub Tiles use Intel 3 — meaning the entire package is built on Intel's own foundry nodes with no external dependency.
How much cache does Diamond Rapids have?
Each base tile features a 320MB shared L3 cache accessible by its four core chiplets; with four base tiles in the package, total last-level cache reaches up to 1.28GB.
How does Diamond Rapids compare to AMD's EPYC Venice?
Wccftech reports that a 256-core Diamond Rapids SKU would match AMD EPYC Venice's top-end 256-core EPYC 9996, though AMD's Zen 6 chips are reportedly already in volume production on a 2nm node ahead of Diamond Rapids' planned 2027 launch.
